SH7080_09 Datasheet, PDF (1220/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 21 Pin Function Controller (PFC)
21.2 Usage Notes
1. In this LSI, the same function is available as a multiplexed function on multiple pins. This
approach is intended to increase the number of selectable pin functions and to allow the easier
design of boards. If two or more pins are specified for one function, however, there are two
cautions shown below.
⎯ When the pin function is input
Signals input to several pins are formed as one signal through OR or AND logic and the
signal is transmitted into the LSI. Therefore, a signal that differs from the input signals may
be transmitted to the LSI depending on the input signals in other pins that have the same
functions. Table 21.22 shows the transmit forms of input functions allocated to several
pins. When using one of the functions shown below in multiple pins, use it with care of
signal polarity considering the transmit forms.
Table 21.22 Transmit Forms of Input Functions Allocated to Multiple Pins
OR Type
AND Type
SCK0, SCK3, RXD0, RXD3,
IRQ0 to IRQ7, DREQ0, DREQ1, BREQ,
TIOC3AS to TIOC3DS, TIOC4AS to TIOC4DS, WAIT, ADTRG, POE4 to POE8
TIC5U, TIC5V, TIC5W, TIC5US, TIC5VS, TIC5WS
OR type: Signals input to several pins are formed as one signal through OR logic and the
signal is transmitted into the LSI.
AND type: Signals input to several pins are formed as one signal through AND logic and
the signal is transmitted into the LSI.
⎯ When the pin function is output
Each selected pin can output the same function.
2. When the port input is switched from a low level to the DREQ or the IRQ edge for the pins
that are multiplexed with input/output and DREQ or IRQ, the corresponding edge is detected.
3. Do not set functions other than those specified in tables 21.17 to 21.20. Otherwise, correct
operation cannot be guaranteed.
4. PFC setting in single-chip mode (MCU operating mode 3)
In single-chip mode, do not set the PFC to select address bus, data bus, bus control, or the
BREQ, BACK, CK, DACK, or TEND signals. If they are selected, address bus signals
function as high- or low-level outputs, data bus signals function as high-impedance outputs,
and the other output signals function as high-level outputs. As BREQ and WAIT function as
inputs, do not leave them open. However, the bus-mastership-request inputs and external waits
are disabled.
Rev. 4.00 Dec. 15, 2009 Page 1160 of 1558
REJ09B0181-0400