SH7080_09 Datasheet, PDF (203/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 7 User Break Controller (UBC)
7.3.5 Break Data Mask Register A (BDMRA) (Only in F-ZTAT Version)
BDMRA is a 32-bit readable/writable register. BDMRA specifies bits masked in the break data
specified by BDRA.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BDMA31 BDMA30 BDMA29 BDMA28 BDMA27 BDMA26 BDMA25 BDMA24 BDMA23 BDMA22 BDMA21 BDMA20 BDMA19 BDMA18 BDMA17 BDMA16
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
BDMA15 BDMA14 BDMA13 BDMA12 BDMA11 BDMA10 BDMA9 BDMA8 BDMA7 BDMA6 BDMA5 BDMA4 BDMA3 BDMA2 BDMA1 BDMA0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 0 BDMA31 to All 0
BDMA 0
R/W Break Data Mask A
Specifies bits masked in the break data of channel A
specified by BDRA (BDA31 to BDA0).
0: Break data BDAn of channel A is included in the
break condition
1: Break data BDAn of channel A is masked and is not
included in the break condition
Note: n = 31 to 0
Notes: 1. Specify an operand size when including the value of the data bus in the break condition.
2. When the byte size is selected as a break condition, the same byte data must be set in
bits 15 to 8 and 7 to 0 in BDMRA as the break mask data in BDRA.
Rev. 4.00 Dec. 15, 2009 Page 143 of 1558
REJ09B0181-0400