SH7080_09 Datasheet, PDF (194/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 6 Interrupt Controller (INTC)
6.8.2
Handling Interrupt Request Signals as Sources for DMAC Activation, but Not
CPU Interrupts and DTC Activation
1. Select DMAC activation sources. Then, CPU interrupts and DTC activation sources are
masked regardless of the settings in the interrupt priority registers and the DTC registers.
2. When an interrupt occurs, an activation request is sent to the DMAC.
3. The DMAC clears the interrupt source when starting transfer.
6.8.3
Handling Interrupt Request Signals as Sources for DTC Activation, but Not CPU
Interrupts and DMAC Activation
1. Do not select DMAC activation sources.
2. For DTC, set the corresponding DTCE bits to 1 and clear the DISEL bits to 0.
3. When an interrupt occurs, an activation request is sent to the DTC.
4. When completing a data transfer, the DTC clears the activation source. No interrupt request is
sent to the CPU because the DTCE bit is held at 1.
5. However, when the transfer counter value = 0, the DTCE bit is cleared to 0 and an interrupt
request is sent to the CPU.
6. The CPU performs the necessary end processing in the interrupt handling routine.
6.8.4
Handling Interrupt Request Signals as Sources for CPU Interrupts, but Not DTC
and DMAC Activation
1 Do not select DMAC activation sources.
2. For DTC, clear the corresponding DTCE bits to 0.
3. When an interrupt occurs, an interrupt request is sent to the CPU.
4. The CPU clears the interrupt source and performs the necessary processing in the interrupt
handling routine.
6.9 Usage Note
The interrupt source flag should be cleared in the interrupt handler. To ensure that an interrupt
source that should have been cleared is not inadvertently accepted again, read the interrupt source
flag after it has been cleared, confirm that it has been cleared, and then execute an RTE
instruction.
Rev. 4.00 Dec. 15, 2009 Page 134 of 1558
REJ09B0181-0400