SH7080_09 Datasheet, PDF (928/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 17 Synchronous Serial Communication Unit (SSU)
Initial
Bit
Bit Name Value R/W
Description
3
TEIE
0
R/W
Transmit End Interrupt Enable
When this bit is set to 1, a SSTEI interrupt request is
enabled.
2
TIE
0
R/W
Transmit Interrupt Enable
When this bit is set to 1, a SSTXI interrupt request is
enabled.
1
RIE
0
R/W
Receive Interrupt Enable
When this bit is set to 1, an SSRXI interrupt request
and an SSOEI interrupt request are enabled.
0
CEIE
0
R/W
Conflict Error Interrupt Enable
When this bit is set to 1, a SSCEI interrupt request is
enabled.
Rev. 4.00 Dec. 15, 2009 Page 868 of 1558
REJ09B0181-0400