SH7080_09 Datasheet, PDF (537/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Initial
Bit
Bit Name Value R/W Description
0
CMFW5
0
R/(W)*¹ Compare Match/Input Capture Flag W5
Status flag that indicates the occurrence of TGRW_5
input capture or compare match.
[Setting conditions]
• When TCNTW_5 = TGRW_5 and TGRW_5 is
functioning as output compare register
• When TCNTW_5 value is transferred to TGRW_5 by
input capture signal and TGRW_5 is functioning as
input capture register
• When TCNTW_5 value is transferred to TGRW_5 and
TGRW_5 is functioning as a register for measuring
the pulse width of the external input signal. The
transfer timing is specified by the IOC bits in timer I/O
control register W_5 (TIORW_5).*²
[Clearing conditions]
• When DTC is activated by a TGIW_5 interrupt and
the DISEL bit of MRB in DTC is 0
• When 0 is written to CMFW5 after reading CMFW5 =
1
Notes: 1. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
2. The transfer timing is specified by the IOC bit in timer I/O control registers
U_5/V_5/W_5 (TIORU_5, TIORV_5, TIORW_5).
Rev. 4.00 Dec. 15, 2009 Page 477 of 1558
REJ09B0181-0400