SH7080_09 Datasheet, PDF (482/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 10 Direct Memory Access Controller (DMAC)
10.5.4 Access to DMAC and DTC Registers through DMAC
Do not access the DMAC or DTC registers through DMAC operation. Do not access the DMAC
registers through DTC operation.
10.5.5 Note on SCI as DMAC Activation Source
When the TXI interrupt in SCI is specified as a DMAC activation source, the TEND flag in the
SCI must not be used as the transfer end flag.
10.5.6 CHCR Setting
Before modifying the CHCR setting, be sure to clear the DE bit in the respective channel.
10.5.7 Note on Multiple Channel Activation
Do not use the same on-chip request in multiple channels.
10.5.8 Note on Transfer Request Input
Transfer requests must be input after DMAC settings are completed.
10.5.9 Conflict between NMI Interrupt and DMAC Activation
When a conflict occurs between the generation of the NMI interrupt and the DMAC activation, the
NMI interrupt has priority. Thus the NMI bit is set to 1 and the DMAC is not activated.
It takes 1 × Bcyc + 3× Pcyc for determining DMAC stop by NMI, 3 × Bcyc for determining
DMAC activation by DREQ, and 1 × Pcyc for determining DMAC activation by peripheral
modules (Bcyc is the external bus clock cycle, and Pcyc is the peripheral clock cycle).
Rev. 4.00 Dec. 15, 2009 Page 422 of 1558
REJ09B0181-0400