SH7080_09 Datasheet, PDF (196/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 7 User Break Controller (UBC)
Figure 7.1 shows a block diagram of the UBC.
LDB
Access
control
IDB
IAB LAB
Access
comparator
Address
comparator
Data
comparator
Channel A
Access
comparator
Address
comparator
BBRA
BARA
BAMRA
BDRA
BDMRA
BBRB
BARB
BAMRB
Internal bus
Data
comparator
Channel B
PC trace
Control
BDRB
BDMRB
BETR
BRSR
BRDR
BRCR
CPU state
signals
User break interrupt request
[Legend]
BBRA:
BARA:
BAMRA:
BDRA:
BDMRA:
BBRB:
BARB:
BAMRB:
Break bus cycle register A
Break address register A
Break address mask register A
Break data register A
Break data mask register A
Break bus cycle register B
Break address register B
Break address mask register B
BDRB:
BDMRB:
BETR:
BRSR:
BRDR:
BRCR:
Break data register B
Break data mask register B
Execution times break register
Branch source register
Branch destination register
Break control register
Figure 7.1 Block Diagram of UBC
Rev. 4.00 Dec. 15, 2009 Page 136 of 1558
REJ09B0181-0400