SH7080_09 Datasheet, PDF (72/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 1 Overview
11
NC
PA15
Vcc
Vss
(FWE*¹)
EXTAL
XTAL
PD0
PD3
Vcc
Vss
NC
10 PE1 PE0 PLLVss PB4 MD0 MD1 Vss PD4 PD6 PD8 PD9
9 PE4 PE3 RES VCL NMI NC PD1 PD5 NC PD10 PD12
8 PF1 PF0 Vss PE2 PB5 NC PD2 PD7 PD11 PD13 PD15
7 PF4 PF5 PF3 PF2
6 PF6 PF7 AVss AVref
5 NC AVcc Vss PE6
P-LFBGA-112*³
(Top view)
PD14 PB6 NC PB7
PB8 PA5 PA3 PA4
PA10 PA9 PA7 PA8
4 Vcc PE7 PE10 Vss PC4 PC11 VCL PA14 PA12 Vcc Vss
3 PE8 PE12 NC NC PC5 PC8 PC14 PB1 PB2 WDTOVF PA13
2 PE13 PE14 PC0 PC2 PC7 PC10 PC13 PC15 NC
PB9 Vss
(ASEMD0*²)
1 NC PE15 PC1 PC3 PC6 PC9 PC12 Vcc PB0 Vss NC
INDEX
A
B
C
D
E
F
G
H
J
K
L
Notes: 1. This pin is fixed to Vss in the mask ROM version and is used as the FWE input pin in the F-ZTAT version.
2. This pin is for the E10A emulator. It is fixed to VCC in the mask ROM version and is used as the ASEMD0
input pin in the F-ZTAT version.
3. The multiplexing of pin functions is the same as for the TQFP1414-100. For details on the pin-multiplexed
functions, see the manual for the TQFP1414-100.
Figure 1.6 Pin Assignments of SH7083 (P-LFBGA-112)
Rev. 4.00 Dec. 15, 2009 Page 12 of 1558
REJ09B0181-0400