SH7080_09 Datasheet, PDF (484/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 10 Direct Memory Access Controller (DMAC)
Start DMA transfer
Disable serial receive (RE = 0 in SCSCR) [1]
Clear serial receive error flag
[2]
Disable DMA transfers (DE = 0)
Clear DMA transfer end state (clear TE)
Interrupt source flag set to 1?
RDRF = 1 in SCSSR?
No
Yes
[3]
Dummy transfer
Clear DMAC error flag
Enable DMAC operation (DME = 1)
DMAC initial settings
Enable serial receive and
receive data full interrupt
[4]
(RE = 1 and RIE = 1 in SCSCR)
Enable DMA transfers (DE = 1)
[1] [1] Disable serial receive so no interrupt (RXI)
occurs during the transfer sequence.
[2] Clear the serial receive error flag. At this point,
do not clear the interrupt source flag (RDRF in
SCSSR).
[3] If the interrupt source flag has been set to 1,
perform a dummy transfer to clear it.
[4] After enabling serial receive and the receive
data full interrupt (RE = 1 and RIE = 1 in
SCSCR), enable DMA transfers (DE = 1).
[5] Wait for the DMA transfer to end. If the DEI
interrupt is enabled (IE = 1), a DEI interrupt will
be generated when the DMA transfer ends.
[6] Disable DMA transfers (DE = 0).
[7] Clear the DMA transfer end state (clear TE).
[8] To continue DMA transfer operation, reset the
DMAC. No dummy transfer is needed in this
case.
[9] Disable the receive data full interrupt (RIE = 0
in SCSCR) to disable interrupt requests.
No
DMA transfer end?
[5]
TE = 1?
Yes
Disable DMA transfers (DE = 0)
[6]
Clear DMA transfer end state (clear TE) [7]
Continue DMA transfer?
No
Disable serial receive and
receive data full interrupt
(RE = 0 and RIE = 0 in SCSCR)
Yes
[8]
[9]
Disable DMAC operation (DME = 0)
DMA transfer end
Figure 10.22 Example DMA Transfer Sequence in Peripheral Module Request Mode (RXI)
Rev. 4.00 Dec. 15, 2009 Page 424 of 1558
REJ09B0181-0400