SH7080_09 Datasheet, PDF (253/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 8 Data Transfer Controller (DTC)
1st Transfer
2nd Transfer
Transfer
Transfer
Transfer
Mode
CHNE CHNS RCHNE DISEL Counter*¹ CHNE CHNS RCHNE DISEL Counter*¹ DTC Transfer
Block
0
⎯
⎯
0
Not 0
⎯
⎯
⎯
⎯
⎯
Ends at 1st
transfer
0
⎯
⎯
0
0
0
⎯
⎯
1
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Ends at 1st
transfer
Interrupt request
to CPU
1
0
⎯
⎯
⎯
0
⎯
⎯
0
Not 0
Ends at 2nd
transfer
0
⎯
⎯
0
0
0
⎯
⎯
1
⎯
Ends at 2nd
transfer
Interrupt request
to CPU
1
1
⎯
0
⎯
⎯
⎯
⎯
⎯
⎯
Ends at 1st
transfer
1
1
⎯
1
Not 0
⎯
⎯
⎯
⎯
⎯
Ends at 1st
transfer
Interrupt request
to CPU
1
1
⎯
1
0
0
⎯
⎯
0
Not 0
Ends at 2nd
transfer
0
⎯
⎯
0
0
0
⎯
⎯
1
⎯
Ends at 2nd
transfer
Interrupt request
to CPU
Notes: 1. CRA in normal mode transfer, CRAL in repeat transfer mode, or CRB in block transfer
mode
2. When the contents of the CRAH is written to the CRAL in repeat transfer mode
Rev. 4.00 Dec. 15, 2009 Page 193 of 1558
REJ09B0181-0400