SH7080_09 Datasheet, PDF (1605/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Item
17.4.5 SSU Mode
(3) Data Reception
Page
886
(4) Data
889
Transmission/Reception
17.4.6 SCS Pin Control 891
and Conflict Error
Figure 17.11 Conflict
Error Detection Timing
(After Transfer End)
17.4.7 Clock
895
Synchronous
Communication Mode
(3) Data Reception
Revision (See Manual for Details)
Description amended
To resume the reception, clear the ORER bit to 0.
When setting the SSU to slave mode to perform continuous
reception, read SSRDR before starting the next receive
operation. If the next receive operation starts before SSRDR
is read and RDRF is cleared to 0, and SSRDR is read before
reception completes, CE in SSSR is set to 1 after the
completion of reception.
In addition, if the next receive operation starts before SSRDR
is read and RDRF is cleared to 0, and SSRDR is not read
until after reception completes, the receive data is discarded
even though neither CE nor ORER in SSSR is set to 1.
Description amended
When starting the transfer, confirm that the TEND, RDRF,
and ORER bits are cleared to 0 before setting the TE or RE
bit to 1.
If the value of RDRF is 1 when the 8th clock rises, ORER in
SSSR is set to 1, an overrun error occurs, and reception
halts. Receive operation is not possible while ORER is set to
1. To restart reception, first clear ORER to 0.
Figure amended
Pφ
SCS
(Hi-Z)
MSS
Internal signal for
transfer enable
CE
Transfer
end
Conflict error detection period
Description amended
The RDRF bit is automatically cleared to 0 by reading
SSRDR.
When setting the SSU to slave mode to perform continuous
reception, read SSRDR before starting the next receive
operation. If the next receive operation starts before SSRDR
is read and RDRF is cleared to 0, the integrity of subsequent
data cannot be guaranteed.
Rev. 4.00 Dec. 15, 2009 Page 1545 of 1558
REJ09B0181-0400