SH7080_09 Datasheet, PDF (236/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 8 Data Transfer Controller (DTC)
Initial
Bit Bit Name Value
R/W
5
DISEL
Undefined ⎯
4
DTS
Undefined ⎯
3, 2 DM[1:0] Undefined ⎯
1, 0 ⎯
Undefined ⎯
[Legend]
x: Don't care
Description
DTC Interrupt Select
When this bit is set to 1, an interrupt request is generated
to the CPU every time a data transfer or a block transfer
ends. When this bit is set to 0, a CPU interrupt request is
only generated when the specified number of data
transfers end.
Note: This bit should be cleared to 0 when the I²C2 is
selected as an activation source.
DTC Transfer Mode Select
Specifies either the source or destination as repeat or
block area during repeat or block transfer mode.
0: Specifies the destination as repeat or block area
1: Specifies the source as repeat or block area
Destination Address Mode 1 and 0
Specify a DAR operation after a data transfer.
0x: DAR is fixed
(DAR writeback is skipped)
10: DAR is incremented after a transfer
(by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and
Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10)
11: SAR is decremented after a transfer
(by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and
Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10)
Reserved
The write value should always be 0.
Rev. 4.00 Dec. 15, 2009 Page 176 of 1558
REJ09B0181-0400