SH7080_09 Datasheet, PDF (1040/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 20 Compare Match Timer (CMT)
20.3 Operation
20.3.1 Interval Count Operation
When an internal clock is selected with bits CKS1 and CKS0 in CMCSR and the STR bit in
CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in
CMCNT and CMCOR match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set
to 1. When the CMIE bit in CMCSR is set to 1, a compare match interrupt (CMI) is requested.
CMCNT then starts counting up again from H'0000.
Figure 20.2 shows the operation of the compare match counter.
CMCNT value
CMCOR
Counter cleared by compare
match with CMCOR
H'0000
Time
Figure 20.2 Counter Operation
20.3.2 CMCNT Count Timing
One of four internal clocks (Pφ/8, Pφ/32, Pφ/128, and Pφ/512) obtained by dividing the Pφ clock
can be selected with bits CKS1 and CKS0 in CMCSR. Figure 20.3 shows the timing.
Peripheral operating
clock (Pφ)
Count clock
CMCNT
Nth
clock
(N + 1)th
clock
N
Figure 20.3 Count Timing
N+1
Rev. 4.00 Dec. 15, 2009 Page 980 of 1558
REJ09B0181-0400