SH7080_09 Datasheet, PDF (1042/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 20 Compare Match Timer (CMT)
20.5 Usage Notes
20.5.1 Module Standby Mode Setting
The CMT operation can be disabled or enabled using the standby control register. The initial
setting is for CMT operation to be halted. Access to a register is enabled by clearing module
standby mode. For details, refer to section 26, Power-Down Modes.
20.5.2 Conflict between Write and Compare-Match Processes of CMCNT
When the compare match signal is generated in the T2 cycle while writing to CMCNT, clearing
CMCNT has priority over writing to it. In this case, CMCNT is not written to. Figure 20.5 shows
the timing to clear the CMCNT counter.
Peripheral operating
clock (Pφ)
CMCSR write cycle
T1
T2
Address
CMCNT
Internal write
Counter clear
CMCNT
N
H'0000
Figure 20.5 Conflict between Write and Compare-Match Processes of CMCNT
Rev. 4.00 Dec. 15, 2009 Page 982 of 1558
REJ09B0181-0400