SH7080_09 Datasheet, PDF (944/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 17 Synchronous Serial Communication Unit (SSU)
(1) When 8-bit data length is selected (SSTDR0 is valid) with CPOS = 0 and CPHS = 0
SCS
1 frame
1 frame
SSCK
SSO
TDRE
Bit Bit Bit Bit Bit Bit Bit Bit
01234567
SSTDR0
(LSB first transmission)
Bit Bit Bit Bit Bit Bit Bit Bit
76543210
SSTDR0
(MSB first transmission)
TEND
LSI operation
TXI interrupt
generated
User operation Data written to SSTDR0
TEI interrupt
generated
TXI interrupt
generated
Data written to SSTDR0
TEI interrupt
generated
(2) When 16-bit data length is selected (SSTDR0 and SSTDR1 are valid) with CPOS = 0 and CPHS = 0
SCS
1 frame
SSCK
SSO
(LSB first)
SSO
(MSB first)
TDRE
Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit
0123456701234567
SSTDR1
SSTDR0
Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit
76543210 76543210
SSTDR0
SSTDR1
TEND
LSI operation
TXI interrupt generated
User operation Data written to SSTDR0 and SSTDR1
TEI interrupt generated
(3) When 32-bit data length is selected (SSTDR0 to SSTDR3 are valid) with CPOS = 0 and CPHS = 0
SCS
1 frame
SSCK
SSO
(LSB first)
SSO
(MSB first)
TDRE
Bit _to Bit
0
7
SSTDR 3
Bit _to Bit
0
7
SSTDR2
Bit _to Bit
0
7
SSTDR1
Bit _to Bit
0
7
SSTDR0
Bit _to Bit
7
0
SSTDR0
Bit _to Bit
7
0
SSTDR1
Bit _to Bit
7
0
SSTDR2
Bit _to Bit
7
0
SSTDR3
TEND
LSI operation
TXI interrupt generated TEI interrupt generated
User operation Data written to SSTDR0 to SSTDR3
Figure 17.5 Example of Transmission Operation (SSU Mode)
Rev. 4.00 Dec. 15, 2009 Page 884 of 1558
REJ09B0181-0400