SH7080_09 Datasheet, PDF (972/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 18 I²C Bus Interface 2 (I²C2)
18.3.4 I²C Bus Interrupt Enable Register (ICIER)
ICIER is an 8-bit readable/writable register that enables or disables interrupt sources and
acknowledge bits, sets acknowledge bits to be transferred, and confirms acknowledge bits
received.
Bit: 7
TIE
Initial value: 0
R/W: R/W
6
TEIE
0
R/W
5
4
3
RIE NAKIE STIE
0
0
0
R/W R/W R/W
2
1
0
ACKE ACKBR ACKBT
0
0
0
R/W R R/W
Initial
Bit
Bit Name Value R/W Description
7
TIE
0
R/W Transmit Interrupt Enable
When the TDRE bit in ICSR is set to 1 or 0, this bit
enables or disables the transmit data empty interrupt
(IITXI).
0: Transmit data empty interrupt request (IITXI) is
disabled.
1: Transmit data empty interrupt request (IITXI) is
enabled.
6
TEIE
0
R/W Transmit End Interrupt Enable
This bit enables or disables the transmit end interrupt
(IITEI) at the rising of the ninth clock while the TDRE bit
in ICSR is 1. IITEI can be canceled by clearing the
TEND bit or the TEIE bit to 0.
0: Transmit end interrupt request (IITEI) is disabled.
1: Transmit end interrupt request (IITEI) is enabled.
5
RIE
0
R/W Receive Interrupt Enable
RIE enables or disables the receive data full interrupt
request (IIRXI) when receive data is transferred from
ICDRS to ICDRR and the RDRF bit in ICSR is set to 1.
IIRXI can be canceled by clearing the RDRF or RIE bit
to 0.
0: Receive data full interrupt request (IIRXI) are
disabled.
1: Receive data full interrupt request (IIRXI) are
enabled.
Rev. 4.00 Dec. 15, 2009 Page 912 of 1558
REJ09B0181-0400