SH7080_09 Datasheet, PDF (24/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

22.4.2 Port D Data Registers H and L (PDDRH and PDDRL)...................................... 1193
22.4.3 Port D Port Registers H and L (PDPRH and PDPRL)........................................ 1196
22.5 Port E ............................................................................................................................... 1199
22.5.1 Register Descriptions.......................................................................................... 1203
22.5.2 Port E Data Registers H and L (PEDRH and PEDRL) ....................................... 1203
22.5.3 Port E Port Registers H and L (PEPRH and PEPRL) ......................................... 1207
22.6 Port F ............................................................................................................................... 1211
22.6.1 Register Descriptions.......................................................................................... 1212
22.6.2 Port F Data Register L (PFDRL) ........................................................................ 1212
Section 23 Flash Memory................................................................................1215
23.1 Features............................................................................................................................ 1215
23.2 Overview.......................................................................................................................... 1217
23.2.1 Block Diagram.................................................................................................... 1217
23.2.2 Operating Mode .................................................................................................. 1218
23.2.3 Mode Comparison .............................................................................................. 1220
23.2.4 Flash Memory Configuration.............................................................................. 1221
23.2.5 Block Division .................................................................................................... 1222
23.2.6 Programming/Erasing Interface .......................................................................... 1223
23.3 Input/Output Pins............................................................................................................. 1225
23.4 Register Descriptions ....................................................................................................... 1225
23.4.1 Registers ............................................................................................................. 1225
23.4.2 Programming/Erasing Interface Registers .......................................................... 1228
23.4.3 Programming/Erasing Interface Parameters ....................................................... 1235
23.4.4 RAM Emulation Register (RAMER).................................................................. 1250
23.5 On-Board Programming Mode ........................................................................................ 1252
23.5.1 Boot Mode .......................................................................................................... 1252
23.5.2 User Program Mode............................................................................................ 1256
23.5.3 User Boot Mode.................................................................................................. 1266
23.6 Protection......................................................................................................................... 1271
23.6.1 Hardware Protection ........................................................................................... 1271
23.6.2 Software Protection............................................................................................. 1272
23.6.3 Error Protection .................................................................................................. 1272
23.7 Flash Memory Emulation in RAM .................................................................................. 1274
23.8 Usage Notes ..................................................................................................................... 1277
23.8.1 Switching between User MAT and User Boot MAT.......................................... 1277
23.8.2 Interrupts during Programming/Erasing ............................................................. 1278
23.8.3 Other Notes......................................................................................................... 1281
23.9 Supplementary Information ............................................................................................. 1283
Rev. 4.00 Dec. 15, 2009 Page xxii of lviii
REJ09B0181-0400