SH7080_09 Datasheet, PDF (258/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 8 Data Transfer Controller (DTC)
8.5.5 Block Transfer Mode
In block transfer mode, data are transferred in block units in response to a single activation
request. Either the transfer source or the transfer destination is designated as a block area by the
DTS bit in MRB.
The block size is 1 to 256 bytes (1 to 256 words, or 1 to 256 longwords). When the block data
transfer of one block ends, the block size counter (CRAL) and address register (SAR when DTS =
1 or DAR when DTS = 0) specified as the block area is restored to the initial state. The other
address register is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be
specified. When the specified number of transfers ends, an interrupt is requested to the CPU.
Table 8.8 lists the register function in block transfer mode. Figure 8.8 shows the memory map in
block transfer mode.
Table 8.8 Register Function in Block Transfer Mode
Register Function
Written Back Value
SAR
Source address
DTS = 0: Incremented/decremented/fixed*
DTS = 1: SAR initial value
DAR
Destination address
DTS = 0: DAR initial value
DTS = 1: Incremented/decremented/fixed*
CRAH Block size storage
CRAH
CRAL Block size counter
CRAH
CRB
Block transfer counter
CRB − 1
Note: * Transfer information writeback is skipped.
Rev. 4.00 Dec. 15, 2009 Page 198 of 1558
REJ09B0181-0400