SH7080_09 Datasheet, PDF (1341/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 23 Flash Memory
23.8.3 Other Notes
1. Download time of on-chip program
The programming program that includes the initialization routine and the erasing program that
includes the initialization routine are each 3 kbytes or less. Accordingly, when the CPU clock
frequency is 20 MHz, the download for each program takes approximately 10 ms at maximum.
2. User branch processing intervals
The intervals for executing the user branch processing differs in programming and erasing. The
processing phase also differs. Table 23.11 lists the maximum intervals for initiating the user
branch processing when the CPU clock frequency is 80 MHz.
Table 23.11 Initiation Intervals of User Branch Processing
Processing Name
Programming
Erasing
Maximum Interval
Approximately 2 ms
Approximately 15 ms
However, when operation is done with CPU clock of 80 MHz, maximum values of the time until
first user branch processing are as shown in table 23.12.
Table 23.12 Initial User Branch Processing Time
Processing Name
Programming
Erasing
Max.
Approximately 2 ms
Approximately 15 ms
3. Write to flash-memory related registers by DMAC or DTC
While an instruction in on-chip RAM is being executed, the DMAC or DTC can write to the
SCO bit in FCCS that is used for a download request or FMATS that is used for MAT
switching. Make sure that these registers are not accidentally written to, otherwise an on-chip
program may be downloaded and destroy RAM or a MAT switchover may occur and the CPU
get out of control.
4. State in which interrupts are ignored
In the following modes or period, interrupt requests are ignored; they are not executed and the
interrupt sources are not retained.
⎯ Boot mode
⎯ Programmer mode
Rev. 4.00 Dec. 15, 2009 Page 1281 of 1558
REJ09B0181-0400