SH7080_09 Datasheet, PDF (421/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
Table 9.31 Minimum Number of Idle Cycles during DMAC Single Address Mode Transfer
to the Normal Space Interface from the External Device with DACK
(1) Transfer from the external device with DACK to the normal space interface
BSC Register Setting*³
CSnWCR.WM
Setting
1
0
1
0
1
0
1
0
1
0
CMNCR.DMAIWA CMNCR.DMAIW
Setting
Idle Setting
0
⎯
0
⎯
1
0
1
0
1
1
1
1
1
2
1
2
1
4
1
4
Minimum Number of Idle Cycles
When Access
Size is Greater
than Bus
Width*¹
When Access Size
is Less than or
Equal to Bus
Width*²
0
1*⁵
1
1
0
1*⁵
1
1
1
1
1
1
2
2
2
2
4
4
4
4
Rev. 4.00 Dec. 15, 2009 Page 361 of 1558
REJ09B0181-0400