SH7080_09 Datasheet, PDF (1296/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 23 Flash Memory
Table 23.6 Usable Parameters and Target Modes
Name of
Parameter
Pro-
Abbrevia- Down- Initiali- gram-
Initial
tion
load zation ming Erasure R/W Value
Allocation
Download pass/fail DPFR √
—
——
result
R/W Undefined On-chip
RAM*
Flash pass/fail
FPFR
—
√
result
√
√
R/W Undefined R0 of CPU
Flash
FPEFEQ —
√
programming/
erasing frequency
control
——
R/W Undefined R4 of CPU
Flash user branch FUBRA —
√
address set
——
R/W Undefined R5 of CPU
Flash multipurpose FMPAR —
—
address area
√
—
R/W Undefined R5 of CPU
Flash multipurpose FMPDR —
—
data destination
area
√
—
R/W Undefined R4 of CPU
Flash erase block FEBS
—
—
select
—√
R/W Undefined R4 of CPU
Note: * One byte of start address of download destination specified by FTDAR
(1) Download Control
The on-chip program is automatically downloaded by setting the SCO bit to 1. The on-chip
RAM area to be downloaded is the area as much as 3 kbytes starting from the start address
specified by FTDAR. For the address map of the on-chip RAM, see figure 23.10.
The download control is set by using the programming/erasing interface registers. The return
value is given by the DPFR parameter.
(a) Download pass/fail result parameter (DPFR: one byte of start address of on-chip RAM
specified by FTDAR)
This parameter indicates the return value of the download result. The value of this
parameter can be used to determine if downloading is executed or not. Since the
confirmation whether the SCO bit is set to 1 is difficult, the certain determination must be
performed by setting one byte of the start address of the on-chip RAM area specified by
FTDAR to a value other than the return value of download (for example, H'FF) before the
download start (before setting the SCO bit to 1). For the checking method of download
results, see section 23.5.2 (2), Programming Procedure in User Program Mode.
Rev. 4.00 Dec. 15, 2009 Page 1236 of 1558
REJ09B0181-0400