SH7080_09 Datasheet, PDF(55/1622 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

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SH7080_09 Datasheet, PDF (55/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

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Table 15.3 SCSMR Settings...................................................................................................... 744

Table 15.4 Bit Rates and SCBRR Settings in Asynchronous Mode (1).................................... 745

Table 15.5 Bit Rates and SCBRR Settings in Asynchronous Mode (2).................................... 746

Table 15.6 Bit Rates and SCBRR Settings in Asynchronous Mode (3).................................... 747

Table 15.7 Bit Rates and SCBRR Settings in Clock Synchronous Mode (1)............................ 748

Table 15.8 Bit Rates and SCBRR Settings in Clock Synchronous Mode (2)............................ 749

Table 15.9 Bit Rates and SCBRR Settings in Clock Synchronous Mode (3)............................ 750

Table 15.10 Maximum Bit Rates for Various Frequencies with Baud Rate Generator

(Asynchronous Mode)............................................................................................. 751

Table 15.11 Maximum Bit Rates with External Clock Input (Asynchronous Mode) ................. 752

Table 15.12 Maximum Bit Rates with External Clock Input (Clock Synchronous Mode) ......... 753

Table 15.13 SCSMR Settings and SCI Communication Formats ............................................... 755

Table 15.14 SCSMR and SCSCR Settings and SCI Clock Source Selection ............................. 755

Table 15.15 Serial Transfer Formats (Asynchronous Mode) ...................................................... 757

Table 15.16 Receive Errors and Error Conditions ...................................................................... 765

Table 15.17 SCI Interrupt Sources .............................................................................................. 782

Table 15.18 SCSSR Status Flag Values and Transfer of Received Data .................................... 784

Section 16 Serial Communication Interface with FIFO (SCIF)

Table 16.1 Pin Configuration .................................................................................................... 791

Table 16.2 Register Configuration ............................................................................................ 792

Table 16.3 SCSMR Settings...................................................................................................... 811

Table 16.4 Bit Rates and SCBRR Settings in Asynchronous Mode ......................................... 812

Table 16.5 Bit Rates and SCBRR Settings in Asynchronous Mode ......................................... 813

Table 16.6 Bit Rates and SCBRR Settings in Asynchronous Mode ......................................... 814

Table 16.7 Bit Rates and SCBRR Settings in Clock Synchronous Mode ................................. 815

Table 16.8 Bit Rates and SCBRR Settings in Clock Synchronous Mode ................................. 816

Table 16.9 Bit Rates and SCBRR Settings in Clock Synchronous Mode ................................. 817

Table 16.10 Maximum Bit Rates for Various Frequencies with Baud Rate Generator

(Asynchronous Mode)............................................................................................. 818

Table 16.11 Maximum Bit Rates with External Clock Input (Asynchronous Mode) ................. 819

Table 16.12 Maximum Bit Rates with External Clock Input (Clock Synchronous Mode) ......... 820

Table 16.13 SCSMR Settings and SCIF Communication Formats ............................................. 830

Table 16.14 SCSMR and SCSCR Settings and SCIF Clock Source Selection ........................... 830

Table 16.15 Serial Communication Formats (Asynchronous Mode) .......................................... 832

Table 16.16 SCIF Interrupt Sources............................................................................................ 850

Section 17 Synchronous Serial Communication Unit (SSU)

Table 17.1 Pin Configuration .................................................................................................... 861

Table 17.2 Register Configuration ............................................................................................ 862

Rev. 4.00 Dec. 15, 2009 Page liii of lviii

REJ09B0181-0400

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