SH7080_09 Datasheet, PDF (204/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 7 User Break Controller (UBC)
7.3.6 Break Address Register B (BARB)
BARB is a 32-bit readable/writable register. BARB specifies the address used as a break condition
in channel B. Control bits CDB1 and CDB0 in BBRB select one of the two address buses for
break condition B.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BAB31 BAB30 BAB29 BAB28 BAB27 BAB26 BAB25 BAB24 BAB23 BAB22 BAB21 BAB20 BAB19 BAB18 BAB17 BAB16
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
BAB15 BAB14 BAB13 BAB12 BAB11 BAB10 BAB9 BAB8 BAB7 BAB6 BAB5 BAB4 BAB3 BAB2 BAB1 BAB0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 0 BAB31 to All 0
BAB 0
R/W Break Address B
Stores an address which specifies a break condition in
channel B.
If the I bus or L bus is selected in BBRB, an IAB or LAB
address is set in BAB31 to BAB0.
Rev. 4.00 Dec. 15, 2009 Page 144 of 1558
REJ09B0181-0400