SH7080_09 Datasheet, PDF (912/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 16 Serial Communication Interface with FIFO (SCIF)
CTS
Reset
R
QD
CTSIO
C
Bit 5
SPTRW
Reset
R
QD
CTSDT
C
Bit 4
SPTRW
Internal data bus
Modem control enable
signal*
CTS signal
[Legend]
SPTRW: SCSPTR write
Note: * The modem control function is specified for the CTS pin by setting the MCE bit in SCFCR.
Figure 16.20 CTSIO Bit, CTSDT bit, and CTS Pin
Reset
R
Bit 3
QD
SCKIO
C
SPTRW
Internal data bus
SCK
Reset
R
QD
SCKDT
C
Bit 2
SPTRW
Clock output enable signal*
Sirial clock output signal*
Serial clock input signal*
Serial input enable signal*
[Legend]
SPTRW: SCSPTR write
Note: * These signals control the SCK pin according to the settings of the C/A bit in SCSMR
and bits CKE1 and CKE0 in SCSCR.
Figure 16.21 SCKIO Bit, SCKDT bit, and SCK Pin
Rev. 4.00 Dec. 15, 2009 Page 852 of 1558
REJ09B0181-0400