SH7080_09 Datasheet, PDF (380/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
Single Read: A read access ends in one cycle when the data bus width is larger than or equal to
access size. This is called single read. As the burst length is set to 1 in SDRAM burst read/single
write mode, only the required data is output. Consequently, no unnecessary bus cycles are
generated.
Figure 9.19 shows the single read basic timing.
CK
A25 to A0
A12/A11*¹
CSn
RASL, RASU
CASL, CASU
RDWR
DQMxx
D31 to D0
BS
DACKn*²
Tr
Tc1
Td1
Tde
Tap
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.19 Single Read Basic Timing (Auto-Precharge)
Rev. 4.00 Dec. 15, 2009 Page 320 of 1558
REJ09B0181-0400