SH7080_09 Datasheet, PDF (852/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 16 Serial Communication Interface with FIFO (SCIF)
16.3 Register Descriptions
The SCIF has the following registers. These registers specify the data format and bit rate, and
control the transmitter and receiver sections.
Table 16.2 Register Configuration
Register Name
Abbr.
R/W
Serial mode register_3
SCSMR_3 R/W
Bit rate register_3
SCBRR_3 R/W
Serial control register_3
SCSCR_3 R/W
Transmit FIFO data register_3 SCFTDR_3 W
Serial status register_3
SCFSR_3 R/W
Receive FIFO data register_3 SCFRDR_3 R
FIFO control register_3
SCFCR_3 R/W
FIFO data count register_3 SCFDR_3 R
Serial port register_3
SCSPTR_3 R/W
Line status register_3
SCLSR_3 R/W
Initial Value Address
H'0000
H'FFFFC180
H'FF
H'FFFFC182
H'0000
H'FFFFC184
H'xx
H'FFFFC186
H'0060
H'FFFFC188
H'xx
H'FFFFC18A
H'0000
H'FFFFC18C
H'0000
H'FFFFC18E
H'00xx
H'FFFFC190
H'0000
H'FFFFC192
Access Size
16
8
16
8
16
8
16
16
16
16
16.3.1 Receive Shift Register (SCRSR)
SCRSR receives serial data. Data input at the RXD pin is loaded into SCRSR in the order
received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received,
it is automatically transferred to SCFRDR, the receive FIFO data register. The CPU cannot read or
write to SCRSR directly.
Bit: 7
6
5
4
3
2
1
0
Initial value: -
-
-
-
-
-
-
-
R/W: -
-
-
-
-
-
-
-
Rev. 4.00 Dec. 15, 2009 Page 792 of 1558
REJ09B0181-0400