SH7080_09 Datasheet, PDF (344/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
1
DMMTU1 0
R/W Enable Burst-Mode DMAC Transfer with TGIA_1
Activation Source
Setting this bit to 1 enables burst-mode DMA transfer
triggered by the TGIA_1 interrupt from MTU2.
0: DMA transfer in burst mode is disabled when TGIA_1
is the activation source.
1: DMA transfer in burst mode is enabled when TGIA_1
is the activation source.
Note: Clear this bit during DMA transfer in cycle-steal
mode.
0
DMMTU0 0
R/W Enable Burst-Mode DMAC Transfer with TGIA_0
Activation Source
Setting this bit to 1 enables burst-mode DMA transfer
triggered by the TGIA_0 interrupt from MTU2.
0: DMA transfer in burst mode is disabled when TGIA_0
is the activation source.
1: DMA transfer in burst mode is enabled when TGIA_0
is the activation source.
Note: Clear this bit during DMA transfer in cycle-steal
mode.
Rev. 4.00 Dec. 15, 2009 Page 284 of 1558
REJ09B0181-0400