SH7080_09 Datasheet, PDF (265/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 8 Data Transfer Controller (DTC)
Table 8.10 Number of Cycles Required for Each Execution State
Object to be Accessed
On-Chip
RAM*¹/ROM*²
On-Chip I/O Registers
External Devices*⁵
Bus width
32 bits
8 bits*⁴
16 bits
8 bits 16 bits 32 bits
Access cycles
1Bφ to 3Bφ*¹*² 2Pφ
2Pφ
2Bφ 2Bφ 2Bφ
Execu- Vector read S_I
1Bφ to 3Bφ*¹*² ⎯
⎯
9Bφ 5Bφ 3Bφ
tion
status
Transfer information read S_J 1Bφ to 3Bφ*¹
⎯
⎯
9Bφ 5Bφ 3Bφ
Transfer information write S_k 1Bφ to 3Bφ*¹ ⎯
⎯
2Bφ*⁶ 2Bφ*⁶ 2Bφ*⁶
Byte data read S_L
1Bφ to 3Bφ*¹ 1Bφ + 2Pφ*³ 1Bφ + 2Pφ*³ 3Bφ 3Bφ 3Bφ
Word data read S_L
1Bφ to 3Bφ*¹ ⎯
1Bφ + 2Pφ*³ 5Bφ 3Bφ 3Bφ
Longword data read S_L
1Bφ to 3Bφ*¹ ⎯
1Bφ + 4Pφ*³ 9Bφ 5Bφ 3Bφ
Byte data write S_M
1Bφ to 3Bφ*¹ 1Bφ + 2Pφ*³ 1Bφ + 2Pφ*³ 2Bφ*⁶ 2Bφ*⁶ 2Bφ*⁶
Word data write S_M
1Bφ to 3Bφ*¹ ⎯
1Bφ + 2Pφ*³ 2Bφ*⁶ 2Bφ*⁶ 2Bφ*⁶
Longword data write S_M
1Bφ to 3Bφ*¹ ⎯
1Bφ + 4Pφ*³ 2Bφ*⁶ 2Bφ*⁶ 2Bφ*⁶
Internal operation S_N
1
Notes: 1. Values for on-chip RAM. Number of cycles varies depending on the ratio of Iφ:Bφ.
Iφ:Bφ = 1:1
Iφ:Bφ = 1:1/2
Iφ:Bφ = 1:1/3
Iφ:Bφ = 1:1/4 or less
Read
3Bφ
2Bφ
2Bφ
1Bφ
Write
3Bφ
1Bφ
1Bφ
1Bφ
2. Values for on-chip ROM. Number of cycles varies depending on the ratio of Iφ:Bφ.and
are the same as on-chip RAM. Only vector read is possible.
3. The values in the table are those for the fastest case. Depending on the state of the
internal bus, replace 1Bφ by 1Pφ in a slow case.
4. This applies to the I²C2.
5. Values are different depending on the BSC register setting. The values in the table are
the sample for the case with no wait cycles and the WM bit in CSnWCR = 1.
6. Values are different depending on the bus state.
The number of cycles increases when many external wait cycles are inserted in the
case where writing is frequently executed, such as block transfer, and when the
external bus is in use because the write buffer cannot be used efficiently in such cases.
For details on the write buffer, see section 9.5.14 (2), Access in View of LSI Internal
Bus Master.
Rev. 4.00 Dec. 15, 2009 Page 205 of 1558
REJ09B0181-0400