SH7080_09 Datasheet, PDF (365/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
Address Multiplexing: An address multiplexing is specified so that SDRAM can be connected
without external address multiplexing circuitry according to the setting of bits BSZ[1:0] in
CSnBCR, and AxROW[1:0] and AxCOL[1:0] in SDCR. Tables 9.20 to 9.25 show the relationship
between the settings of bits BSZ[1:0], AxROW[1:0], and AxCOL[1:0] and the bits output at the
address pins. Do not specify those bits in the manner other than this table, otherwise the operation
of this LSI is not guaranteed. A25 to A18 are not multiplexed and the original values of address
are always output at these pins.
When the data bus width is 16 bits (BSZ[1:0] = B'10), the A0 pin of SDRAM specifies a word
address. Therefore, connect this A0 pin of SDRAM to the A1 pin of this LSI, then A1 pin to the
A2 pin, and so on. When the data bus width is 32 bits (BSZ[1:0] = B'11), the A0 pin of SDRAM
specifies a longword address. Therefore, connect this A0 pin of SDRAM to the A2 pin of this LSI,
then A1 pin to the A3 pin, and so on.
Rev. 4.00 Dec. 15, 2009 Page 305 of 1558
REJ09B0181-0400