SH7080_09 Datasheet, PDF (53/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 11.1 MTU2 Functions ..................................................................................................... 428
Table 11.2 Pin Configuration .................................................................................................... 433
Table 11.3 Register Configuration ............................................................................................ 434
Table 11.4 CCLR0 to CCLR2 (Channels 0, 3, and 4)............................................................... 439
Table 11.5 CCLR0 to CCLR2 (Channels 1 and 2).................................................................... 439
Table 11.6 TPSC0 to TPSC2 (Channel 0)................................................................................. 440
Table 11.7 TPSC0 to TPSC2 (Channel 1)................................................................................. 440
Table 11.8 TPSC0 to TPSC2 (Channel 2)................................................................................. 441
Table 11.9 TPSC0 to TPSC2 (Channels 3 and 4)...................................................................... 441
Table 11.10 TPSC1 and TPSC0 (Channel 5) .............................................................................. 442
Table 11.11 Setting of Operation Mode by Bits MD0 to MD3................................................... 444
Table 11.12 TIORH_0 (Channel 0)............................................................................................. 447
Table 11.13 TIORL_0 (Channel 0) ............................................................................................. 448
Table 11.14 TIOR_1 (Channel 1)................................................................................................ 449
Table 11.15 TIOR_2 (Channel 2)................................................................................................ 450
Table 11.16 TIORH_3 (Channel 3)............................................................................................. 451
Table 11.17 TIORL_3 (Channel 3) ............................................................................................. 452
Table 11.18 TIORH_4 (Channel 4)............................................................................................. 453
Table 11.19 TIORL_4 (Channel 4) ............................................................................................. 454
Table 11.20 TIORH_0 (Channel 0)............................................................................................. 455
Table 11.21 TIORL_0 (Channel 0) ............................................................................................. 456
Table 11.22 TIOR_1 (Channel 1)................................................................................................ 457
Table 11.23 TIOR_2 (Channel 2)................................................................................................ 458
Table 11.24 TIORH_3 (Channel 3)............................................................................................. 459
Table 11.25 TIORL_3 (Channel 3) ............................................................................................. 460
Table 11.26 TIORH_4 (Channel 4)............................................................................................. 461
Table 11.27 TIORL_4 (Channel 4) ............................................................................................. 462
Table 11.28 TIORU_5, TIORV_5, and TIORW_5 (Channel 5) ................................................. 463
Table 11.29 Setting of Transfer Timing by BF1 and BF0 Bits ................................................... 485
Table 11.30 Output Level Select Function.................................................................................. 498
Table 11.31 Output Level Select Function.................................................................................. 499
Table 11.32 Setting of Bits BF1 and BF0 ................................................................................... 501
Table 11.33 TIOC4D Output Level Select Function................................................................... 501
Table 11.34 TIOC4B Output Level Select Function................................................................... 502
Table 11.35 TIOC4C Output Level Select Function................................................................... 502
Table 11.36 TIOC4A Output Level Select Function................................................................... 502
Table 11.37 TIOC3D Output Level Select Function................................................................... 502
Table 11.38 TIOC4B Output Level Select Function................................................................... 503
Table 11.39 Output level Select Function ................................................................................... 506
Rev. 4.00 Dec. 15, 2009 Page li of lviii
REJ09B0181-0400