SH7080_09 Datasheet, PDF (42/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Figure 17.10 Conflict Error Detection Timing (Before Transfer) ............................................... 890
Figure 17.11 Conflict Error Detection Timing (After Transfer End) .......................................... 891
Figure 17.12 Example of Initial Settings in Clock Synchronous Communication Mode............ 892
Figure 17.13 Example of Transmission Operation
(Clock Synchronous Communication Mode)......................................................... 893
Figure 17.14 Flowchart Example of Transmission Operation
(Clock Synchronous Communication Mode)......................................................... 894
Figure 17.15 Example of Reception Operation
(Clock Synchronous Communication Mode)......................................................... 895
Figure 17.16 Flowchart Example of Data Reception
(Clock Synchronous Communication Mode)......................................................... 896
Figure 17.17 Flowchart Example of Simultaneous Transmission/Reception
(Clock Synchronous Communication Mode)......................................................... 897
Section 18 I²C Bus Interface 2 (I²C2)
Figure 18.1 Block Diagram of I²C Bus Interface 2.................................................................... 902
Figure 18.2 External Circuit Connections of I/O Pins............................................................... 903
Figure 18.3 I²C Bus Formats ..................................................................................................... 920
Figure 18.4 I²C Bus Timing....................................................................................................... 920
Figure 18.5 Master Transmit Mode Operation Timing (1)........................................................ 922
Figure 18.6 Master Transmit Mode Operation Timing (2)........................................................ 922
Figure 18.7 Master Receive Mode Operation Timing (1) ......................................................... 924
Figure 18.8 Master Receive Mode Operation Timing (2) ......................................................... 925
Figure 18.9 Slave Transmit Mode Operation Timing (1).......................................................... 927
Figure 18.10 Slave Transmit Mode Operation Timing (2).......................................................... 928
Figure 18.11 Slave Receive Mode Operation Timing (1) ........................................................... 929
Figure 18.12 Slave Receive Mode Operation Timing (2) ........................................................... 930
Figure 18.13 Clock Synchronous Serial Transfer Format ........................................................... 930
Figure 18.14 Transmit Mode Operation Timing ......................................................................... 931
Figure 18.15 Receive Mode Operation Timing........................................................................... 933
Figure 18.16 Operation Timing For Receiving One Byte ........................................................... 933
Figure 18.17 Block Diagram of Noise Filter ............................................................................... 934
Figure 18.18 Sample Flowchart for Master Transmit Mode ....................................................... 935
Figure 18.19 Sample Flowchart for Master Receive Mode......................................................... 936
Figure 18.20 Sample Flowchart for Slave Transmit Mode ......................................................... 937
Figure 18.21 Sample Flowchart for Slave Receive Mode ........................................................... 938
Figure 18.22 The Timing of the Bit Synchronous Circuit........................................................... 941
Section 19 A/D Converter (ADC)
Figure 19.1 Block Diagram of A/D Converter (for One Module)............................................. 946
Rev. 4.00 Dec. 15, 2009 Page xl of lviii
REJ09B0181-0400