SH7080_09 Datasheet, PDF (1529/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 28 Electrical Characteristics
28.3.13 I²C Bus Interface 2 (I²C2) Timing
Table 28.18 I²C Bus Interface 2 (I²C2) Timing
Conditions: V_CC = 3.0 V to 3.6 V or 4.0 V to 5.5 V, AV_CC = 4.0 V to 5.5 V, AV_ref = 4.0 V to AV_CC,
V_SS = PLLV_SS = AV_SS = 0 V, T_a = –20°C to +85°C (consumer applications),
T_a = –40°C to +85°C (industrial applications)
Item
Symbol Min.
Typ.
SCL input cycle time
t
SCL
SCL input high pulse width t_SCLH
SCL input low pulse width
t_SCLL
SCL and SDA input fall time t
Sf
SCL and SDA input spike t
SP
pulse removal time
12 t + 600 ⎯
pcyc
3 t_pcyc + 300 ⎯
5 t_pcyc + 300 ⎯
⎯
⎯
⎯
⎯
SDA input bus free time
t_BUF
5
⎯
Start condition input hold time t_STAH
3
⎯
Repeated start condition input t
3
⎯
STAS
setup time
Halt condition input setup
t_STOS
3
⎯
time
Data input setup time
t_SDAS
1 t_pcyc + 20 ⎯
Data input hold time
t_SDAH
0
⎯
SCL and SDA capacity load C_b
0
⎯
SCL and SDA output fall time t_Sf
⎯
⎯
Note: t_pcyc indicates the peripheral clock (Pφ) cycle.
Max.
⎯
⎯
⎯
300
1t
pcyc
⎯
⎯
⎯
⎯
⎯
⎯
400
250
Reference
Unit Figure
ns
Figure 28.60
ns
ns
ns
ns
t_pcyc
t_pcyc
t
pcyc
t_pcyc
ns
ns
pF
ns
Rev. 4.00 Dec. 15, 2009 Page 1469 of 1558
REJ09B0181-0400