English
Language : 

SH7080_09 Datasheet, PDF (35/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family
Figure 11.23 Cascaded Operation Example (c) ........................................................................... 532
Figure 11.24 Cascaded Operation Example (d)........................................................................... 533
Figure 11.25 Example of PWM Mode Setting Procedure ........................................................... 536
Figure 11.26 Example of PWM Mode Operation (1) .................................................................. 536
Figure 11.27 Example of PWM Mode Operation (2) .................................................................. 537
Figure 11.28 Example of PWM Mode Operation (3) .................................................................. 538
Figure 11.29 Example of Phase Counting Mode Setting Procedure............................................ 539
Figure 11.30 Example of Phase Counting Mode 1 Operation ..................................................... 540
Figure 11.31 Example of Phase Counting Mode 2 Operation ..................................................... 541
Figure 11.32 Example of Phase Counting Mode 3 Operation ..................................................... 542
Figure 11.33 Example of Phase Counting Mode 4 Operation ..................................................... 543
Figure 11.34 Phase Counting Mode Application Example ......................................................... 545
Figure 11.35 Procedure for Selecting Reset-Synchronized PWM Mode .................................... 547
Figure 11.36 Reset-Synchronized PWM Mode Operation Example
(When TOCR’s OLSN = 1 and OLSP = 1)............................................................ 548
Figure 11.37 Block Diagram of Channels 3 and 4 in Complementary PWM Mode ................... 551
Figure 11.38 Example of Complementary PWM Mode Setting Procedure................................. 552
Figure 11.39 Complementary PWM Mode Counter Operation................................................... 553
Figure 11.40 Example of Complementary PWM Mode Operation ............................................. 555
Figure 11.41 Example of Operation without Dead Time ............................................................ 558
Figure 11.42 Example of PWM Cycle Updating......................................................................... 559
Figure 11.43 Example of Data Update in Complementary PWM Mode..................................... 561
Figure 11.44 Example of Initial Output in Complementary PWM Mode (1).............................. 562
Figure 11.45 Example of Initial Output in Complementary PWM Mode (2).............................. 563
Figure 11.46 Example of Complementary PWM Mode Waveform Output (1) .......................... 565
Figure 11.47 Example of Complementary PWM Mode Waveform Output (2) .......................... 565
Figure 11.48 Example of Complementary PWM Mode Waveform Output (3) .......................... 566
Figure 11.49 Example of Complementary PWM Mode 0% and 100% Waveform Output (1) ... 566
Figure 11.50 Example of Complementary PWM Mode 0% and 100% Waveform Output (2) ... 567
Figure 11.51 Example of Complementary PWM Mode 0% and 100% Waveform Output (3) ... 567
Figure 11.52 Example of Complementary PWM Mode 0% and 100% Waveform Output (4) ... 568
Figure 11.53 Example of Complementary PWM Mode 0% and 100% Waveform Output (5) ... 568
Figure 11.54 Example of Toggle Output Waveform Synchronized with PWM Output.............. 569
Figure 11.55 Counter Clearing Synchronized with Another Channel ......................................... 570
Figure 11.56 Timing for Synchronous Counter Clearing ............................................................ 571
Figure 11.57 Example of Procedure for Setting Output Waveform Control at Synchronous
Counter Clearing in Complementary PWM Mode................................................. 572
Figure 11.58 Example of Synchronous Clearing in Dead Time during Up-Counting
(Timing (3) in Figure 11.56; Bit WRE of TWCR in MTU2 is 1) .......................... 573
Rev. 4.00 Dec. 15, 2009 Page xxxiii of lviii
REJ09B0181-0400