SH7080_09 Datasheet, PDF (907/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 16 Serial Communication Interface with FIFO (SCIF)
Receiving Serial Data (Clock Synchronous Mode): Figures 16.15 and 16.16 show a sample
flowchart for receiving serial data. When switching from asynchronous mode to clock
synchronous mode without SCIF initialization, make sure that ORER, PER, and FER are cleared
to 0.
Start of reception
Read ORER flag in SCLSR
ORER = 1?
No
Read RDF flag in SCFSR
Yes
[1]
Error handling
[2]
[1] Receive error handling:
Read the ORER flag in SCLSR to
identify any error, perform the appropriate
error handling, then clear the ORER flag
to 0. Transmission/reception cannot be
resumed while the ORER flag is set to 1.
[2] SCIF status check and receive data read:
Read SCFSR and check that RDF = 1,
then read the receive data in SCFRDR,
and clear the RDF flag to 0. The transition
of the RDF flag from 0 to 1 can also be
identified by an RXIF interrupt.
No
RDF = 1?
Yes
Read receive data in
SCFRDR, and clear RDF
[3]
flag in SCFSR to 0
No
All data received?
[3] Serial reception continuation procedure:
To continue serial reception, read at least
the receive trigger number of receive data
bytes from SCFRDR, read 1 from the
RDF flag, then clear the RDF flag to 0.
The number of receive data bytes in
SCFRDR can be ascertained by reading
from the lower 8 bits of SCFDR.
Yes
Clear RE bit in SCSCR to 0
End of reception
Figure 16.15 Sample Flowchart for Receiving Serial Data (1)
Error handling
No
ORER = 1?
Yes
Overrun error handling
Clear ORER flag in SCLSR to 0
End
Figure 16.16 Sample Flowchart for Receiving Serial Data (2)
Rev. 4.00 Dec. 15, 2009 Page 847 of 1558
REJ09B0181-0400