SH7080_09 Datasheet, PDF (542/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Initial
Bit
Bit Name Value R/W Description
3
CE1A
0
R/W Clear Enable 1A
Enables or disables counter clearing when the TGFA
flag of TSR_1 in the MTU2 is set.
0: Disables counter clearing by the TGFA flag in TSR_1
1: Enables counter clearing by the TGFA flag in TSR_1
2
CE1B
0
R/W Clear Enable 1B
Enables or disables counter clearing when the TGFB
flag of TSR_1 in the MTU2 is set.
0: Disables counter clearing by the TGFB flag in TSR_1
1: Enables counter clearing by the TGFB flag in TSR_1
1
CE2A
0
R/W Clear Enable 2A
Enables or disables counter clearing when the TGFA
flag of TSR_2 in the MTU2 is set.
0: Disables counter clearing by the TGFA flag in TSR_2
1: Enables counter clearing by the TGFA flag in TSR_2
0
CE2B
0
R/W Clear Enable 2B
Enables or disables counter clearing when the TGFB
flag of TSR_2 in the MTU2 is set.
0: Disables counter clearing by the TGFB flag in TSR_2
1: Enables counter clearing by the TGFB flag in TSR_2
Rev. 4.00 Dec. 15, 2009 Page 482 of 1558
REJ09B0181-0400