SH7080_09 Datasheet, PDF (975/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 18 I²C Bus Interface 2 (I²C2)
Initial
Bit
Bit Name Value R/W Description
5
RDRF
0
R/W Receive Data Register Full
[Setting condition]
• When a receive data is transferred from ICDRS to
ICDRR
[Clearing conditions]
• When 0 is written to RDRF after reading RDRF = 1
• When ICDRR is read
• DTC is activated by IIRXI interrupt and the DISEL
bit in MRB of DTC is 0.
4
NACKF
0
R/W No Acknowledge Detection Flag*
[Setting condition]
• When no acknowledge is detected from the receive
device in transmission while the ACKE bit in ICIER
is 1
[Clearing condition]
• When 0 is written to NACKF after reading NACKF
=1
3
STOP
0
R/W Stop Condition Detection Flag
[Setting conditions]
• In master mode, when a stop condition is detected
after frame transfer
• In slave mode, when a stop condition is detected
after the slave address in the first byte that came
following the detection of a start condition have
matched the address set in SAR.
[Clearing condition]
• When 0 is written to STOP after reading STOP = 1
Rev. 4.00 Dec. 15, 2009 Page 915 of 1558
REJ09B0181-0400