SH7080_09 Datasheet, PDF (1541/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Appendix
Pin Function
Pin State
Reset State
Power-Down State
Type
Pin Name
Power-On
Expansion
without ROM
Expansion Single-
Deep
Software Software
8 bits 16 bits ^{with ROM chip Manual Standby Standby}
Bus
Master- Oscillation POE
ship Stop
Function
Sleep Release Detected Used
I/O Port
PD0 to PD8, Z
PD10
I/O
Z
K*¹
I/O I/O
I/O
I/O
PD9,
Z
PD11 to PD15
PE0 to PE3 Z
PE4,
Z
PE6 to PE8,
PE10
I/O
Z
I/O
Z
I/O
Z
Z
I/O I/O
I/O*⁴
Z
(MZIZDL in
HCPCR = 0)
K*¹
(MZIZDL in
HCPCR = 1)
K*¹
I/O I/O
I/O
Z
K*¹
I/O I/O
I/O
I/O
PE12 to PE15 Z
I/O
Z
Z
I/O I/O
I/O*⁵
Z
(MZIZEL in
HCPCR = 0)
K*¹
(MZIZEL in
HCPCR = 1)
PF0 to PF7 Z
I
Z
Z
I
I
I
I
[Legend]
I:
Input
O: Output
H: High-level output
L:
Low-level output
Z:
High-impedance
K:
Input pins become high-impedance, and output pins retain their state.
Notes: 1. Output pins become high-impedance when the HIZ bit in standby control register 6
(STBCR6) is set to 1.
2. Becomes output when the HIZCNT bit in the common control register (CMNCR) is set
to 1.
3. Becomes output when the HIZMEM bit in the common control register (CMNCR) is set
to 1.
4. Becomes high-impedance when the MZIZDL bit in the high-current port control register
(HCPCR) is cleared to 0.
Rev. 4.00 Dec. 15, 2009 Page 1481 of 1558
REJ09B0181-0400