SH7080_09 Datasheet, PDF (829/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 15 Serial Communication Interface (SCI)
Transmitting Serial Data (Clock Synchronous Mode): Figure 15.10 shows a sample flowchart
for transmitting serial data.
Use the following procedure for serial data transmission after enabling the SCI for transmission.
Start of transmission
Read TDRE flag in SCSSR
No
TDRE = 1?
Yes
Write transmit data to SCTDR
and clear TDRE flag
in SCSSR to 0
No
All data transmitted?
Yes
Read TEND flag in SCSSR
No
TEND = 1?
Yes
Clear TE bit in SCSCR to 0
[1] SCI status check and transmit data
write:
Read SCSSR and check that the
TDRE flag is set to 1, then write
transmit data to SCTDR, and clear
the TDRE flag to 0.
[2] Serial transmission continuation
procedure:
To continue serial transmission, read
1 from the TDRE flag to confirm that
writing is possible, then write data to
SCTDR, and then clear the TDRE
flag to 0. Checking and clearing of the
TDRE flag is automatic when the
DMAC or DTC is activated by a
transmit data empty interrupt (TXI)
request, and data is written to
SCTDR.
End of transmission
Figure 15.10 Sample Flowchart for Transmitting Serial Data
Rev. 4.00 Dec. 15, 2009 Page 769 of 1558
REJ09B0181-0400