SH7080_09 Datasheet, PDF (268/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 8 Data Transfer Controller (DTC)
Clock (Bφ)
DTC activation
request 1
DTC activation
request 2
DTC request
Bus release timing
[setting 5]
Bus release timing
[setting 3]
Bus release timing
[setting 4]
Bus release timing
[setting 1]
Bus release timing
[setting 2]
Internal address
RW
RW
Vector
read
Transfer information Data Transfer information Vector
read
transfer
write
read
Transfer information Data Transfer information
read
transfer
write
[Legend]
: Indicates bus release timing.
: Bus mastership is only released for the external access request from the CPU.
Note: DTC request signal indicates the state of internal bus request after the DTC activation source is determined.
Figure 8.16 Example of DTC Operation Timing:
Conflict of Two Activation Requests in Normal Transfer Mode
(Activated by On-Chip Peripheral Module; Iφ: Bφ: Pφ = 1: 1/2: 1/2;
Data Transferred from On-Chip Peripheral Module to On-Chip RAM;
Transfer Information is Written in 3 Cycles)
Rev. 4.00 Dec. 15, 2009 Page 208 of 1558
REJ09B0181-0400