SH7080_09 Datasheet, PDF (274/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 8 Data Transfer Controller (DTC)
8.9.5 Transfer Information Start Address, Source Address, and Destination Address
The transfer information start address to be specified in the vector table should be address 4n.
Transfer information should be placed in on-chip RAM or external memory space.
8.9.6 Access to DMAC or DTC Registers through DTC
Do not access the DMAC or DTC registers by using DTC operation. Do not access the DTC
registers by using DMAC operation.
8.9.7 Notes on IRQ Interrupt as DTC Activation Source
• The IRQ interrupt specified as a DTC activation source must not be used to cancel software
standby mode.
• The IRQ edge input in software standby mode must not be specified as a DTC activation
source.
• When a low level on the IRQ pin is to be detected, if the end of DTC transfer is used to request
an interrupt to the CPU (transfer counter = 0 or DISEL = 1), the IRQ signal must be kept low
until the CPU accepts the interrupt.
8.9.8 Notes on SCI and SCIF as DTC Activation Sources
• When the TXI interrupt from the SCI is specified as a DTC activation source, the TEND flag
in the SCI must not be used as the transfer end flag.
• When the TXIF interrupt from the SCIF is specified as a DTC activation source, the TEND
flag in the SCIF must not be used as the transfer end flag.
8.9.9 Clearing Interrupt Source Flag
The interrupt source flag set when the DTC transfer is completed should be cleared in the interrupt
handler in the same way as for general interrupt source flags. For details, refer to section 6.9,
Usage Note.
Rev. 4.00 Dec. 15, 2009 Page 214 of 1558
REJ09B0181-0400