SH7080_09 Datasheet, PDF (193/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 6 Interrupt Controller (INTC)
Interrupt source
Interrupt controller
Interrupt priority
determination
Interrupt request to CPU
Decode
DTC
DMAC
CHCR
RS bits 3 to 0
DMAC activation
request
Interrupt source
flag clear
DTCER
DTCE clear
Interrupt source flag clear by DTC
DTC activation
request
DTCECLR
Transfer end
Interrupt source
flag clear
by DMAC
Figure 6.6 On-Chip Module Interrupt Control Block Diagram
6.8.1
Handling Interrupt Request Signals as Sources for DTC Activation and CPU
Interrupts, but Not DMAC Activation
1. Do not select DMAC activation sources.
2. For DTC, set the corresponding DTCE bits and DISEL bits to 1.
3. When an interrupt occurs, an activation request is sent to the DTC.
4. When completing a data transfer, the DTC clears the DTCE bit to 0 and sends an interrupt
request to the CPU. The activation source is not cleared.
5. The CPU clears the interrupt source in the interrupt handling routine then checks the transfer
counter value. When the transfer counter value is not 0, the CPU sets the DTCE bit to 1 and
allows the next data transfer. If the transfer counter value = 0, the CPU performs the necessary
end processing in the interrupt processing routine.
Rev. 4.00 Dec. 15, 2009 Page 133 of 1558
REJ09B0181-0400