SH7080_09 Datasheet, PDF (1604/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Item
17.3.5 SS Status
Register (SSSR)
Page
871
17.4.4 Communication 880
Modes and Pin Functions
Table 17.7
Communication Modes
and Pin States of SCS
Pin
Revision (See Manual for Details)
Table amended
Initial
Bit
Bit Name Value R/W
1
RDRF
0
R/W
0
CE
0
R/W
Description
Receive Data Register Full
Indicates whether or not SSRDR contains receive data.
[Setting condition]
• When receive data is transferred from SSTRSR to
SSRDR after successful serial data reception
[Clearing conditions]
• When writing 0 after reading RDRF = 1
• When reading receive data from SSRDR
• When the DTC is activated by an SSRXI interrupt
and receive data is read into SSRDR while the
DISEL bit in MRB of the DTC is 0 (except when
DTC transfer counter value is H'0000)
Conflict/Incomplete Error
Indicates that a conflict error has occurred
when 0 is externally input to the SCS pin with SSUMS
= 0 (SSU mode) and MSS = 1 (master mode).
If the SCS pin level changes to 1 with SSUMS = 0 (SSU
mode) and MSS = 0 (slave mode), an incomplete error
occurs because it is determined that a master device
has terminated the transfer. In addition, when SSUMS =
0 (SSU mode) and MSS = 0 (slave mode) and the next
serial receive operation starts while RDRF = 1, an
incomplete error occurs even if the data received from
SSRDR is read before the completion of reception and
RDRF is cleared to 0 before the SCS pin is set to 1.
Data reception does not continue while the CE bit is set
to 1. Serial transmission also does not continue. Reset
the SSU internal sequencer by setting the SRES bit in
SSCRL to 1 before resuming transfer after incomplete
error.
[Setting conditions]
• When a low level is input to the SCS pin in master
mode (the MSS bit in SSCRH is set to 1)
• When the SCS pin is changed to 1 during transfer in
slave mode (the MSS bit in SSCRH is cleared to 0)
• When in slave mode (MSS = 0 in SSCRH), the next
serial receive operation starts while RDRF = 1, and
data is read from SSRDR before the completion of
reception, after which the SCS pin is set to 1
[Clearing condition]
• When writing 0 after reading CE = 1
Table amended
Communication
Mode
SSUMS
SSU communication 0
mode
Register Setting
MSS
CSS1
0
x
1
0
0
1
1
CSS0
x
0
1
0
1
Pin State
SCS
Input
⎯
⎯
Automatic
input/output
Output
Rev. 4.00 Dec. 15, 2009 Page 1544 of 1558
REJ09B0181-0400