SH7080_09 Datasheet, PDF (1401/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 26 Power-Down Modes
26.6 Deep Software Standby Mode
26.6.1 Transition to Deep Software Standby Mode
This LSI shifts from a program execution state to deep software standby mode by executing the
SLEEP instruction when the STBY bit in STBCR1 is 1 and the STBYMD bit in STBCR6 is 0.
However, deep software standby mode cannot be entered when the bus is released (low-level input
to BREQ pin). Execute the SLEEP instruction after halting the DMAC and DTC. In deep software
standby mode, not only the CPU but also the clock and on-chip peripheral modules halt.
Furthermore, the internal power supply of this LSI is turned off.
The contents of the CPU registers and the data of the on-chip RAM become undefined. The
registers of on-chip peripheral modules are initialized. For details on the pin states in deep
software standby mode, refer to appendix A, Pin States.
The procedure for a transition to deep software standby mode is as follows:
1. Clear the TME bit in the timer control register (WTCSR) of the WDT to 0 to stop the WDT.
2. If the DMAC and DTC are operating, stop their operation.
3. If the bus is released (low-level input to BREQ pin), acquire the bus mastership (high-level
input to BREQ pin).
4. After setting the STBY bit in STBCR1 to 1 and clearing the STBYMD bit in STBCR6 to 0,
execute the SLEEP instruction.
5. Deep software standby mode is entered, the clocks within this LSI are halted, and the internal
power supply of this LSI is turned off.
26.6.2 Canceling Deep Software Standby Mode
Deep software standby mode is canceled by a power-on reset with the RES pin. Keep the RES pin
low until the clock oscillation settles.
Rev. 4.00 Dec. 15, 2009 Page 1341 of 1558
REJ09B0181-0400