SH7080_09 Datasheet, PDF (191/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 6 Interrupt Controller (INTC)
Table 6.4 Interrupt Response Time
Number of Cycles
Item
Peripheral
NMI
IRQ
Modules
Remarks
DMAC/DTC active
⎯
judgement
2 × Bcyc
1 × Pcyc
Interrupt priority decision
and comparison with mask
bits in SR
1 × Icyc + 2 ×
Pcyc
1 × Icyc + 1 ×
Pcyc
1 × Icyc + 2 ×
Pcyc
Wait for completion of
sequence currently being
executed by CPU
X (≥ 0)
X (≥ 0)
X (≥ 0)
The longest sequence is
for interrupt or address-
error exception handling
(X = 7 × Icyc + m1 + m2
+ m3 + m4). If an
interrupt-masking
instruction follows,
however, the time may
be even longer.
Time from start of interrupt
exception handling until
fetch of first instruction of
exception handling routine
starts
8 × Icyc +
m1 + m2 + m3
8 × Icyc +
m1 + m2 + m3
8 × Icyc +
m1 + m2 + m3
Performs the saving PC
and SR, and vector
address fetch.
Interrupt
response
time
Total:
9 × Icyc + 2 ×
Pcyc + m1 + m2
+ m3 + X
9 × Icyc + 1 × 9 × Icyc + 3 ×
Pcyc +2 × Bcyc + Pcyc + m1 + m2
m1 + m2 + m3 + + m3 + X
X
Minimum*: 12 × Icyc +
2 × Pcyc
12 × Icyc +
1 × Pcyc +
2 × Bcyc
12 × Icyc +
3 × Pcyc
SR, PC, and vector table
are all in on-chip RAM.
Maximum:
16 × Icyc +
2 × Pcyc + 2 ×
(m1 + m2 + m3)
+ m4
16 × Icyc +
1 × Pcyc +
2 × Bcyc + 2 ×
(m1 + m2 + m3)
+ m4
16 × Icyc +
3 × Pcyc + 2 ×
(m1 + m2 + m3)
+ m4
Notes: *
In the case that m1 = m2 = m3 = m4 = 1 × Icyc.
m1 to m4 are the number of cycles needed for the following memory accesses.
m1: SR save (longword write)
m2: PC save (longword write)
m3: Vector address read (longword read)
m4: Fetch first instruction of interrupt service routine
Rev. 4.00 Dec. 15, 2009 Page 131 of 1558
REJ09B0181-0400