SH7080_09 Datasheet, PDF (965/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 18 I²C Bus Interface 2 (I²C2)
18.3 Register Descriptions
The I²C bus interface 2 has the following registers. For details on register addresses and register
states during each processing, refer to section 27, List of Registers.
Table 18.2 Register Configuration
Register Name
I²C bus control register 1
I²C bus control register 2
I²C bus mode register
I²C bus interrupt enable
register
I²C bus status register
I²C bus slave address register
I²C bus transmit data register
I²C bus receive data register
NF2CYC register
Abbrevia-
tion
ICCR1
ICCR2
ICMR
ICIER
ICSR
SAR
ICDRT
ICDRR
NF2CYC
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
H'00
H'7D
H'38
H'00
Address
H'FFFFCD80
H'FFFFCD81
H'FFFFCD82
H'FFFFCD83
H'00
H'00
H'FF
H'FF
H'00
H'FFFFCD84
H'FFFFCD85
H'FFFFCD86
H'FFFFCD87
H'FFFFCD88
Access Size
8
8
8
8
8
8
8
8
8
18.3.1 I²C Bus Control Register 1 (ICCR1)
ICCR1 is an 8-bit readable/writable register that enables or disables the I²C bus interface 2,
controls transmission or reception, and selects master or slave mode, transmission or reception,
and transfer clock frequency in master mode.
Bit: 7
6
5
ICE RCVD MST
Initial value: 0
0
0
R/W: R/W R/W R/W
4
TRS
0
R/W
3
0
R/W
2
1
CKS[3:0]
0
0
R/W R/W
0
0
R/W
Initial
Bit
Bit Name Value R/W Description
7
ICE
0
R/W I²C Bus Interface 2 Enable
0: This module is halted.
1: This bit is enabled for transfer operations. (SCL and
SDA pins are bus drive state.)
Rev. 4.00 Dec. 15, 2009 Page 905 of 1558
REJ09B0181-0400