SH7080_09 Datasheet, PDF (218/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 7 User Break Controller (UBC)
7.4 Operation
7.4.1 Flow of the User Break Operation
The flow from setting of break conditions to user break exception processing is described below:
1. The break addresses are set in the break address registers (BARA or BARB). The masked
addresses are set in the break address mask registers (BAMRA or BAMRB). The break data is
set in the break data register (BDRA or BDRB). The masked data is set in the break data mask
register (BDMRA or BDMRB). The bus break conditions are set in the break bus cycle
registers (BBRA or BBRB). Three groups of BBRA or BBRB (L bus cycle/I bus cycle select,
instruction fetch/data access select, and read/write select) are each set. No user break will be
generated if even one of these groups is set with B'00. The respective conditions are set in the
bits of the break control register (BRCR). Make sure to set all registers related to breaks before
setting BBRA or BBRB.
2. When the break conditions are satisfied, the UBC sends a user break interrupt request to the
CPU and sets the L bus condition match flag (SCMFCA or SCMFCB) and the I bus condition
match flag (SCMFDA or SCMFDB) for the appropriate channel.
3. The appropriate condition match flags (SCMFCA, SCMFDA, SCMFCB, and SCMFDB) can
be used to check if the set conditions match or not. The matching of the conditions sets flags,
but they are not reset. Before using them again, 0 must first be written to them and then reset
flags.
4. There is a chance that matches of the break conditions set in channels A and B occur almost at
the same time. In this case, there will be only one user break request to the CPU, but these two
conditions match flags could be both set.
5. When selecting the I bus as the break condition, note the following:
⎯ The CPU, DMAC, and DTC are connected to the I bus. The UBC monitors bus cycles
generated by all bus masters that are selected by the CPA2 to CPA0 bits in BBRA or the
CPB2 to CPB0 bits in BBRB, and compares the conditions for a match.
⎯ I bus cycles (including read fill cycles) resulting from instruction fetches on the L bus by
the CPU are defined as instruction fetch cycles on the I bus, while other bus cycles are
defined as data access cycles.
⎯ The DMAC and DTC only issue data access cycles for I bus cycles.
⎯ If a break condition is specified for the I bus, even when the condition matches in an I bus
cycle resulting from an instruction executed by the CPU, at which instruction the user
break is to be accepted cannot be clearly defined.
Rev. 4.00 Dec. 15, 2009 Page 158 of 1558
REJ09B0181-0400