SH7080_09 Datasheet, PDF (261/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

8.5.7 Operation Timing
Figures 8.10 to 8.15 show the DTC operation timings.
Section 8 Data Transfer Controller (DTC)
Clock (Bφ)
DTC activation
request
DTC request
Internal address
R
W
Vector read
Transfer information
read
Data Transfer information
transfer
write
Note: The DTC request signal indicates the state of internal bus request after the DTC activation source has been determined.
Figure 8.10 Example of DTC Operation Timing:
Normal Transfer Mode or Repeat Transfer Mode
(Activated by On-Chip Peripheral Module; Iφ: Bφ: Pφ =1: 1/2: 1/2;
Data Transferred from On-Chip Peripheral Module to On-Chip RAM;
Transfer Information is Written in 3 Cycles)
Clock (Bφ)
DTC activation
request
DTC request
Internal address
R
W
R
W
Vector read
Transfer information
read
Data
transfer
Transfer information
write
Note: The DTC request signal indicates the state of internal bus request after the DTC activation source has been determined.
Figure 8.11 Example of DTC Operation Timing:
Block Transfer Mode with Block Size = 2
(Activated by On-Chip Peripheral Module; Iφ: Bφ: Pφ =1: 1/2: 1/2;
Data Transferred from On-Chip Peripheral Module to On-Chip RAM;
Transfer Information is Written in 3 Cycles)
Rev. 4.00 Dec. 15, 2009 Page 201 of 1558
REJ09B0181-0400