SH7080_09 Datasheet, PDF (779/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 14 Watchdog Timer (WDT)
14.3.3 Notes on Register Access
The watchdog timer counter (WTCNT) and watchdog timer control/status register (WTCSR) are
more difficult to write to than other registers. The procedure for writing to these registers is given
below.
Writing to WTCNT and WTCSR: These registers must be written by a word transfer
instruction. They cannot be written by a byte or longword transfer instruction. When writing to
WTCNT, set the upper byte to H'5A and transfer the lower byte as the write data, as shown in
figure 14.2. When writing to WTCSR, set the upper byte to H'A5 and transfer the lower byte as
the write data. This transfer procedure writes the lower byte data to WTCNT or WTCSR.
WTCNT write
15
Address: H'FFFFE810
H'5A
87
0
Write data
WTCSR write
15
Address: H'FFFFE812
H'A5
87
0
Write data
Figure 14.2 Writing to WTCNT and WTCSR
Rev. 4.00 Dec. 15, 2009 Page 719 of 1558
REJ09B0181-0400