SH7080_09 Datasheet, PDF (1325/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 23 Flash Memory
(3.4) The return value in the erasing program, FPFR (general register R0) is checked.
(3.5) Determine whether erasure of the necessary blocks has finished.
If more than one block is to be erased, update the FEBS parameter and repeat steps (3.2) to
(3.5). Blocks that have already been erased can be erased again.
(3.6) After erasure finishes, clear FKEY and specify software protection.
If this LSI is restarted by a power-on reset immediately after user MAT erasing has finished,
secure a reset period (period of RES = 0) that is at least as long as the normal 100 μs.
(4) Erasing and Programming Procedure in User Program Mode
By changing the on-chip RAM address of the download destination in FTDAR, the erasing
program and programming program can be downloaded to separate on-chip RAM areas.
Figure 23.13 shows an example of repetitively executing RAM emulation, erasing, and
programming.
1
Start procedure program
Set FTDAR to H'00
(Specify H'FFFF9000 as
download destination)
Download erasing program
Initialize erasing program
Enter RAM emulation mode and
tune data in on-chip RAM
Cancel RAM emulation mode
Erase relevant block
(execute erasing program)
Set FTDAR to H'04
(Specify H'FFFFB000 as
download destination)
Set FMPDR to H'FFFFA000 to
program relevant block
(execute programming program)
Download programming
program
Initialize programming
program
1
Confirm operation
End?
No
Yes
End procedure program
Figure 23.13 Sample Procedure of Repeating RAM Emulation, Erasing, and Programming
(Overview)
Rev. 4.00 Dec. 15, 2009 Page 1265 of 1558
REJ09B0181-0400