SH7080_09 Datasheet, PDF (1485/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 28 Electrical Characteristics
CK
A29 to A0
CSn
RDWR
RD
Read
D31 to D0
Th
T1
Twx
T2
Tf
t_AD1
t_CSD
t_RWD
t_RSD
t_OE
t_ACC
t_RSD
t_RDS1
t_RDH1
Write
WRxx
D31 to D0
BS
DACKn*
TENDn*
t_WDD1
t_WSD1
t_BSD
t_DACD
t_BSD
t_WTH
t_WTH
t_WSD1
WAIT
t_WTS
t_WTS
Note: * The waveform for DACKn and TENDn is when active low is specified.
Figure 28.15 CS Extended Bus Cycle for Normal Space
(SW = 1 Cycle, HW = 1 Cycle, One External Wait Cycle)
t_AD1
t_CSD
t_RWD
t_WDH1
t_DACD
Rev. 4.00 Dec. 15, 2009 Page 1425 of 1558
REJ09B0181-0400